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(parent: 28166a8) | patch
[X86] Simplify some code in lowerV4X128VectorShuffle and lowerV2X128VectorShuffle
authorCraig Topper <craig.topper@intel.com>
Fri, 9 Feb 2018 05:54:36 +0000 (05:54 +0000)
committerCraig Topper <craig.topper@intel.com>
Fri, 9 Feb 2018 05:54:36 +0000 (05:54 +0000)
commitca5841b4e4544f7b5da051a43ea778cb140c2536
tree39e3aa38ad3159e9717025208388a632c7c406d2tree | snapshot
parent28166a877d5e4e886c2c254e8f68197b644b62a6commit | diff
[X86] Simplify some code in lowerV4X128VectorShuffle and lowerV2X128VectorShuffle

Previously we extracted two subvectors and concatenate. But the concatenate will be lowered to two insert subvectors. Then DAG combine will merge once of the inserts and one of the extracts back into the original vector. We might as well just directly use one extract and one insert.

llvm-svn: 324710
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/X86/x86-interleaved-access.ll diff | blob | history
Domain: System / Toolchain;