clk: renesas: div6: Switch to .determine_rate()
authorGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 1 Apr 2021 13:01:36 +0000 (15:01 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 11 May 2021 07:58:13 +0000 (09:58 +0200)
commitc9d1b58b272e272fc7121929e2d0e0755ea1656e
treec2d97e9ce5f6e64e1d5234c2b651909010f3ead3
parent23b04c84e201e82c1929144a2ce1442bd64e77f3
clk: renesas: div6: Switch to .determine_rate()

As the .round_rate() callback returns a long clock rate, it cannot
return clock rates that do not fit in signed long, but do fit in
unsigned long.  Hence switch the DIV6 clocks on SH/R-Mobile and R-Car
SoCs from the old .round_rate() callback to the newer .determine_rate()
callback, which does not suffer from this limitation.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/7fd8c45cd8bf5c6d928ca69c8b669be35b93de09.1617281699.git.geert+renesas@glider.be
drivers/clk/renesas/clk-div6.c