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author	JP Lehr <JanPatrick.Lehr@amd.com>
	Mon, 5 Jun 2023 14:39:50 +0000 (10:39 -0400)
committer	JP Lehr <JanPatrick.Lehr@amd.com>
	Mon, 5 Jun 2023 14:55:58 +0000 (10:55 -0400)
commit	c9998ec145972714d581e19fd1c9cb276b836387
tree	5d50170fedfcdb796ecea47f76b483f7d834d39b	tree \| snapshot
parent	420cf63ead105d024f0dd0e90b67a7ffb1fd64fb	commit \| diff

Revert "[DAGCombine] Make sure combined nodes are added back to the worklist in topological order."

This reverts commit e69fa03ddd85812be3143d79a0359c3e8d43bd45.

This patch lead to build time outs on the AMDGPU OpenMP runtime
buildbot.

115 files changed:

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/ds-alignment.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/ds_write2.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/idot4u.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/idot8s.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/idot8u.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/store-local.128.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/store-local.96.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/addsubcarry-promotion.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/icmp-shift-opt.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/reg_sequence.ll		diff \| blob \| history
llvm/test/CodeGen/Hexagon/autohvx/isel-vpackew.ll		diff \| blob \| history
llvm/test/CodeGen/Hexagon/autohvx/mulh.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/combine-fneg.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/select_const.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/mul.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/pr58511.ll		diff \| blob \| history
llvm/test/CodeGen/SystemZ/pr36164.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-vst3.ll		diff \| blob \| history
llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll		diff \| blob \| history
llvm/test/CodeGen/X86/2012-08-07-CmpISelBug.ll		diff \| blob \| history
llvm/test/CodeGen/X86/addcarry.ll		diff \| blob \| history
llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll		diff \| blob \| history
llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll		diff \| blob \| history
llvm/test/CodeGen/X86/avx512-mask-op.ll		diff \| blob \| history
llvm/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll		diff \| blob \| history
llvm/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll		diff \| blob \| history
llvm/test/CodeGen/X86/bitcast-vector-bool.ll		diff \| blob \| history
llvm/test/CodeGen/X86/const-shift-of-constmasked.ll		diff \| blob \| history
llvm/test/CodeGen/X86/dagcombine-select.ll		diff \| blob \| history
llvm/test/CodeGen/X86/field-extract-use-trunc.ll		diff \| blob \| history
llvm/test/CodeGen/X86/horizontal-sum.ll		diff \| blob \| history
llvm/test/CodeGen/X86/icmp-shift-opt.ll		diff \| blob \| history
llvm/test/CodeGen/X86/insertelement-var-index.ll		diff \| blob \| history
llvm/test/CodeGen/X86/is_fpclass-fp80.ll		diff \| blob \| history
llvm/test/CodeGen/X86/isel-blendi-gettargetconstant.ll		diff \| blob \| history
llvm/test/CodeGen/X86/masked_store.ll		diff \| blob \| history
llvm/test/CodeGen/X86/midpoint-int-vec-512.ll		diff \| blob \| history
llvm/test/CodeGen/X86/movmsk-cmp.ll		diff \| blob \| history
llvm/test/CodeGen/X86/mulvi32.ll		diff \| blob \| history
llvm/test/CodeGen/X86/nontemporal-3.ll		diff \| blob \| history
llvm/test/CodeGen/X86/pmulh.ll		diff \| blob \| history
llvm/test/CodeGen/X86/popcnt.ll		diff \| blob \| history
llvm/test/CodeGen/X86/promote-vec3.ll		diff \| blob \| history
llvm/test/CodeGen/X86/psubus.ll		diff \| blob \| history
llvm/test/CodeGen/X86/shift-mask.ll		diff \| blob \| history
llvm/test/CodeGen/X86/shuffle-strided-with-offset-128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/single_elt_vector_memory_operation.ll		diff \| blob \| history
llvm/test/CodeGen/X86/smax.ll		diff \| blob \| history
llvm/test/CodeGen/X86/smin.ll		diff \| blob \| history
llvm/test/CodeGen/X86/smulo-128-legalisation-lowering.ll		diff \| blob \| history
llvm/test/CodeGen/X86/umax.ll		diff \| blob \| history
llvm/test/CodeGen/X86/umin.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshl-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshl-512.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshl-rot-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshl-rot-512.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshr-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshr-512.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshr-rot-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-fshr-rot-512.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-2.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-2.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-4.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-and-bool.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-and.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-or-bool.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-or.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-reduce-xor.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-rotate-256.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-rotate-512.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-shuffle-concatenation.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-shuffle-sse4a.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vector-zext.ll		diff \| blob \| history
llvm/test/CodeGen/X86/wide-integer-cmp.ll		diff \| blob \| history
llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll		diff \| blob \| history
llvm/test/CodeGen/X86/xaluo128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/xor.ll		diff \| blob \| history
llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll		diff \| blob \| history

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