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ARM: DRA7: emif: Fix DDR init sequence during warm reset
authorLokesh Vutla <lokeshvutla@ti.com>
Thu, 4 Jun 2015 04:38:50 +0000 (10:08 +0530)
committerTom Rini <trini@konsulko.com>
Mon, 15 Jun 2015 14:57:27 +0000 (10:57 -0400)
commitc997da5c53586e0cb220d94179f922e865cffb62
treefa43c37a6848a8b6067694d3d62f246ee15a72e1tree | snapshot
parent2ce6ecaccaa0b1bea31cdbe05f5f5c54d2468db0commit | diff
ARM: DRA7: emif: Fix DDR init sequence during warm reset

Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after
warm reset, emif needs to be configured to bring it back to a known
state. So configure EMIF during warm reset.

Reported-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arch/arm/cpu/armv7/omap-common/emif-common.c diff | blob | history
Domain: System / Kernel;