drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv
authorAkash Goel <akash.goel@intel.com>
Mon, 24 Mar 2014 17:30:07 +0000 (23:00 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 5 Jun 2014 06:52:32 +0000 (08:52 +0200)
commitc98f50628722e2e287656bc7e7492e3d3a0726b8
tree33b44b8f23e23cb8360a2c5a58f9f3a6c9ceeaaa
parent2ab8b458c6a1c784a1edc4308d920f97c0e2a2b8
drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv

For disabling L3 clock gating we need to set bit 25 of MMIO
register 940c. Earlier this was being done by just writing 1
into bit 25 and resetting all other bits.
This patch modifies the routine to read-modify-write of the
register, so that the values of other bits are not destroyed.

v2: Modifying the comments and the patch commit message (Chris)

Signed-off-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sourab Gupta <sourab.gupta@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Apply checkpatch fixup.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_pm.c