projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: d10f173) | patch
[RISCV] Correct the output chain in lowerFixedLengthVectorMaskedLoadToRVV
authorCraig Topper <craig.topper@sifive.com>
Thu, 18 Mar 2021 23:22:19 +0000 (16:22 -0700)
committerCraig Topper <craig.topper@sifive.com>
Thu, 18 Mar 2021 23:34:35 +0000 (16:34 -0700)
commitc9861f722e375c419a07bcb70c54fe1384cd2999
treeda5c143d49ef65302e465e94c07d1d00dcf784fatree | snapshot
parentd10f173f34baa139c4e85be96ff1750d6d689c8ecommit | diff
[RISCV] Correct the output chain in lowerFixedLengthVectorMaskedLoadToRVV

We returned the input chain instead of the output chain from the
new load. This bypasses the load in the chain. I haven't found a
good way to test this yet. IR order prevents my initial attempts
at causing reordering.
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
Domain: System / Toolchain;