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(parent: 335668b) | patch
[SVE] Fix incorrect VT usage when lowering fixed length vector divides.
authorPaul Walker <paul.walker@arm.com>
Tue, 20 Dec 2022 01:39:31 +0000 (01:39 +0000)
committerPaul Walker <paul.walker@arm.com>
Sun, 8 Jan 2023 12:22:05 +0000 (12:22 +0000)
commitc9602e02fc16e8a3fcb6f7b58d8615b04a8fde38
treed3112200fba4a03805ccf17b8d8ca465cdce9865tree | snapshot
parent335668b116439d13c7555616e126acdc608ce59ecommit | diff
[SVE] Fix incorrect VT usage when lowering fixed length vector divides.

Ensure the negation required when lowering negative power-of-two
divides uses the scalable vector container type with the fixed
length result extracted from it.

Fixes: #59647

Differential Revision: https://reviews.llvm.org/D140563
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll diff | blob | history
Domain: System / Toolchain;