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(parent: 808ecf4) | patch
clk: mediatek: add the option for determining PLL source clock
authorChen Zhong <chen.zhong@mediatek.com>
Thu, 5 Oct 2017 03:50:23 +0000 (11:50 +0800)
committerStephen Boyd <sboyd@codeaurora.org>
Thu, 2 Nov 2017 08:07:51 +0000 (01:07 -0700)
commitc955bf3998efa3355790a4d8c82874582f1bc727
tree4df4e73b5bd0d3d4ba1405bdb20950b7b5070308tree | snapshot
parent808ecf4ad087f80c2eee99af67549f05d5315694commit | diff
clk: mediatek: add the option for determining PLL source clock

Since the previous setup always sets the PLL using crystal 26MHz, this
doesn't always happen in every MediaTek platform. So the patch added
flexibility for assigning extra member for determining the PLL source
clock.

Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/mediatek/clk-mtk.h diff | blob | history
drivers/clk/mediatek/clk-pll.c diff | blob | history
Domain: System / Kernel;