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(parent: 6e889b1) | patch
drm/i915: Program VLV/CHV PIPE_MSA_MISC register
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 14 Mar 2023 13:02:50 +0000 (15:02 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 17 Mar 2023 13:05:38 +0000 (15:05 +0200)
commitc931ef0041fe0a7b62b7d15774a831f3bc85713a
treeafeb35e91d4085b2a6037bef59bc5e222e4af1f3tree | snapshot
parent6e889b1ce7f1be2bfcfe39a4bcc82b34380031c4commit | diff
drm/i915: Program VLV/CHV PIPE_MSA_MISC register

VLV/CHV have an extra register to configure some stereo3d
signalling details via DP MSA. Make sure we reset that
register to zero (since we don't do any stereo3d stuff).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230314130255.23273-5-ville.syrjala@linux.intel.com
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
drivers/gpu/drm/i915/display/intel_display.c diff | blob | history
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
Domain: System / Kernel;