GBE: optimize post reg allocation instruction scheduling.
authorZhigang Gong <zhigang.gong@intel.com>
Tue, 20 May 2014 10:38:05 +0000 (18:38 +0800)
committerZhigang Gong <zhigang.gong@intel.com>
Tue, 27 May 2014 02:20:23 +0000 (10:20 +0800)
commitc90c4759119a78f89f27b8a384631adcc5040e78
tree74f41480031083511874bc07e4613927a55ebe54
parente91d0d608a2843942937533b3afb7faee53af591
GBE: optimize post reg allocation instruction scheduling.

To make the post scheduling working better, I relax the frequency of
the calling of expireGRF when doing register allocation. Thus we can
reduce the physical register conflict and doing the post scheduling.

Another optimization is to insert a pre retire for the instruction
to release those WRITE_AFTER_READ dependency. Write after read will
not bring any hazard, so we can release those register as soon as
the instruction scheduled.

The pre register allocation scheduling is quite different than post
schedlulig, for now, just disable it.

The whole patch could get about 10% perfromance gain with luxmark.

Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>
Reviewed-by: "Yang, Rong R" <rong.r.yang@intel.com>
backend/src/backend/gen_insn_gen7_schedule_info.hxx
backend/src/backend/gen_insn_scheduling.cpp
backend/src/backend/gen_insn_selection.cpp
backend/src/backend/gen_reg_allocation.cpp