Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+REG addre...

Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+REG addressing with an assumed offset register.

	PR 22988
opcode	* opcode/aarch64.h (enum aarch64_opnd): Add
	AARCH64_OPND_SVE_ADDR_R.

opcodes	* aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
	instructions with only a base address register.
	* aarch64-opc.c (operand_general_constraint_met_p): Add code to
	handle AARHC64_OPND_SVE_ADDR_R.
	(aarch64_print_operand): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64_dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

gas	* config/tc-aarch64.c (parse_operands): Add code to handle
	AARCH64_OPN_SVE_ADDR_R.
	* testsuite/gas/aarch64/sve.s: Add tests for LDFF1xx instructions
	with an assumed XZR offset address register.
	* testsuite/gas/aarch64/sve.d: Update expected disassembly.