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[RISCV] Add Syntacore SCR1 CPU model
authorDmitrii Petrov <dmitrii.petrov@syntacore.com>
Wed, 14 Dec 2022 08:12:23 +0000 (11:12 +0300)
committerAnton Afanasyev <anton.afanasyev@syntacore.com>
Wed, 14 Dec 2022 08:45:44 +0000 (11:45 +0300)
commitc86a878e8995d54a5b950098e81f0d3bf153aded
tree5e8e0ede70ad426ba7cb3c34ce66c4c3b3a8e36ftree | snapshot
parent8a55264be311bf54ddef0430c712ad51a80a5f7fcommit | diff
[RISCV] Add Syntacore SCR1 CPU model

SCR1 is available at https://github.com/syntacore/scr1

'syntacore-scr1-base' corresponds to SCR1_CFG_RV32IC_BASE,
'syntacore-scr1-max' corresponds to SCR1_CFG_RV32IMC_MAX.

SCR1_CFG_RV32EC_MIN is RV32EC, which is currently unsupported.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139302
clang/test/Driver/riscv-cpus.c diff | blob | history
clang/test/Misc/target-invalid-cpu-note.c diff | blob | history
llvm/include/llvm/Support/RISCVTargetParser.def diff | blob | history
llvm/lib/Target/RISCV/RISCV.td diff | blob | history
llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td [new file with mode: 0644] blob
Domain: System / Toolchain;