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author	Shengchen Kan <shengchen.kan@intel.com>
	Fri, 19 May 2023 14:21:56 +0000 (22:21 +0800)
committer	Shengchen Kan <shengchen.kan@intel.com>
	Fri, 19 May 2023 14:21:56 +0000 (22:21 +0800)
commit	c81a121f3f230cfe468b6def6d2904b4aefb855b
tree	27474657bae28b20540b1ef0b4f6d5cc43206daf	tree \| snapshot
parent	35ff5eba16465bd4116db266c01cbabebd500484	commit \| diff

Revert "Revert "[X86] Remove patterns for ADC/SBB with immediate 8 and optimize during MC lowering, NFCI""

This reverts commit cb16b33a03aff70b2499c3452f2f817f3f92d20d.

In fact, the test https://bugs.chromium.org/p/chromium/issues/detail?id=1446973#c2
already passed after 5586bc539acb26cb94e461438de01a5080513401

63 files changed:

llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp		diff \| blob \| history
llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.h		diff \| blob \| history
llvm/lib/Target/X86/X86CallFrameOptimization.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86DynAllocaExpander.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86FastISel.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86FixupLEAs.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86FrameLowering.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86ISelLowering.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86InstrAVX512.td		diff \| blob \| history
llvm/lib/Target/X86/X86InstrArithmetic.td		diff \| blob \| history
llvm/lib/Target/X86/X86InstrCompiler.td		diff \| blob \| history
llvm/lib/Target/X86/X86InstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86InstructionSelector.cpp		diff \| blob \| history
llvm/lib/Target/X86/X86MCInstLower.cpp		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir		diff \| blob \| history
llvm/test/CodeGen/X86/AMX/amx-greedy-ra-spill-shape.ll		diff \| blob \| history
llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir		diff \| blob \| history
llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir		diff \| blob \| history
llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir		diff \| blob \| history
llvm/test/CodeGen/X86/GlobalISel/select-ext.mir		diff \| blob \| history
llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir		diff \| blob \| history
llvm/test/CodeGen/X86/avxvnni-combine.ll		diff \| blob \| history
llvm/test/CodeGen/X86/cfi-xmm.ll		diff \| blob \| history
llvm/test/CodeGen/X86/extend-set-cc-uses-dbg.ll		diff \| blob \| history
llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir		diff \| blob \| history
llvm/test/CodeGen/X86/leaFixup32.mir		diff \| blob \| history
llvm/test/CodeGen/X86/leaFixup64.mir		diff \| blob \| history
llvm/test/CodeGen/X86/limit-split-cost.mir		diff \| blob \| history
llvm/test/CodeGen/X86/machinesink-debug-inv-0.mir		diff \| blob \| history
llvm/test/CodeGen/X86/optimize-compare.mir		diff \| blob \| history
llvm/test/CodeGen/X86/peephole-fold-testrr.mir		diff \| blob \| history
llvm/test/CodeGen/X86/pr46827.ll		diff \| blob \| history
llvm/test/CodeGen/X86/push-cfi.ll		diff \| blob \| history
llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll		diff \| blob \| history
llvm/test/CodeGen/X86/switch-bit-test-unreachable-default.ll		diff \| blob \| history
llvm/test/CodeGen/X86/switch-lower-peel-top-case.ll		diff \| blob \| history
llvm/test/CodeGen/X86/tail-call-conditional.mir		diff \| blob \| history
llvm/test/CodeGen/X86/tail-merge-after-mbp.mir		diff \| blob \| history
llvm/test/CodeGen/X86/throws-cfi-fp.ll		diff \| blob \| history
llvm/test/CodeGen/X86/twoaddr-dbg-value.mir		diff \| blob \| history
llvm/test/CodeGen/X86/update-terminator-debugloc.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vecloadextract.ll		diff \| blob \| history
llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir		diff \| blob \| history
llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir		diff \| blob \| history
llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir		diff \| blob \| history
llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir		diff \| blob \| history
llvm/test/DebugInfo/MIR/X86/empty-inline.mir		diff \| blob \| history
llvm/test/DebugInfo/MIR/X86/kill-after-spill.mir		diff \| blob \| history
llvm/test/DebugInfo/MIR/X86/live-debug-values-stack-clobber.mir		diff \| blob \| history
llvm/test/DebugInfo/MIR/X86/machinesink-subreg.mir		diff \| blob \| history
llvm/test/DebugInfo/MIR/X86/machinesink.mir		diff \| blob \| history
llvm/test/DebugInfo/MIR/X86/merge-inline-loc4.mir		diff \| blob \| history
llvm/test/DebugInfo/MIR/X86/mlicm-hoist-post-regalloc.mir		diff \| blob \| history
llvm/test/DebugInfo/X86/debug-loc-asan.mir		diff \| blob \| history
llvm/test/DebugInfo/X86/debug-loc-offset.mir		diff \| blob \| history
llvm/test/DebugInfo/X86/location-range.mir		diff \| blob \| history
llvm/test/DebugInfo/X86/machinecse-wrongdebug-hoist.ll		diff \| blob \| history
llvm/test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll		diff \| blob \| history
llvm/test/DebugInfo/assignment-tracking/X86/lower-to-value.ll		diff \| blob \| history
llvm/test/TableGen/x86-fold-tables.inc		diff \| blob \| history
llvm/test/Transforms/SampleProfile/pseudo-probe-twoaddr.ll		diff \| blob \| history
llvm/utils/TableGen/X86ManualFoldTables.def		diff \| blob \| history

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