[X86][Costmodel] Load/store i64/f64 Stride=4 VF=8 interleaving costs
authorRoman Lebedev <lebedev.ri@gmail.com>
Mon, 4 Oct 2021 19:50:11 +0000 (22:50 +0300)
committerRoman Lebedev <lebedev.ri@gmail.com>
Tue, 5 Oct 2021 13:58:57 +0000 (16:58 +0300)
commitc800119c46fb266b7fc75409fd9cbbb1a6d8f72a
tree39758e88dc0cbff6bd2c0aeec8835b8dc63659d5
parent000ce0bfd52bbfe48732f378f5a67f307424552b
[X86][Costmodel] Load/store i64/f64 Stride=4 VF=8 interleaving costs

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/3M3hbq7n8 - for intels `Block RThroughput: =20.0`; for ryzens, `Block RThroughput: =8.0`
So could pick cost of `20`.

For store we have:
https://godbolt.org/z/zvnPYWTx7 - for intels `Block RThroughput: =20.0`; for ryzens, `Block RThroughput: =8.0`
So we could pick cost of `20`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D111076
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll
llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-4.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-4.ll