drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validation
authorRoy Spliet <r.spliet@student.tudelft.nl>
Mon, 9 Jan 2012 05:23:07 +0000 (15:23 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Tue, 13 Mar 2012 07:07:50 +0000 (17:07 +1000)
commitc7c039fd31be82ecb8d48477955e76badd38141a
tree0b527eba7fd021ce99c52d9f744d503d0919849c
parent03ddf04bdb9cc4cdf8edb231b78f031647498314
drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validation

Roy Spliet:
- Implement according to specs
- Simplify
- Make array for mc latency registers

Martin Peres:
- squash and split all the commits from Roy
- rework following Ben Skeggs comments
- add a form of timings validation
- store the initial timings for later use

Ben Skeggs
- merge slightly modified tidy-up patch with this one
- remove perflvl-dropping logic for the moment

Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl>
Signed-off-by: Martin Peres <martin.peres@labri.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nouveau_drv.h
drivers/gpu/drm/nouveau/nouveau_mem.c
drivers/gpu/drm/nouveau/nouveau_pm.c
drivers/gpu/drm/nouveau/nv50_vram.c