TEST mfld pmu: add arch/x86/platform/mfld/pmu.c

TEST mfld pmu: add arch/x86/platform/mfld/pmu.c

From UMG 2.6.35 tree: arch/x86/kernel/mid_pmu.c

commit 30365108003d6d71f508b5cf4429e9588a5928a0
Author: Fengwei Yin <fengwei.yin@intel.com>
Date:   Mon Jul 11 11:16:33 2011 +0800

    Revert "mid_pmu:  do not issue set_command during s3 entry"

    BZ: 4883

    This reverts commit a49316f33d6066dd13d85f577dce84dd0278d4d0.

    Change-Id: If9a8c696f626a7d6d8fcd42da8e1563a5c1bf4f8
    Signed-off-by: Fengwei Yin <fengwei.yin@intel.com>
commit 9f42b0f20930f74e6840a335db62b9089f7176da
Author: Prabu Renganathan <prabu.renganathan@intel.com>
Date:   Fri Jun 17 18:28:36 2011 -0700

    mid_pmu:  pick D0i1 as USB low power state

    BZ: 3497

    HSD: 3337060

    Fix for the Penwell bug where USB only supports D0i1

    Signed-off-by: Prabu Renganathan <prabu.renganathan@intel.com>
    Change-Id: Icb0c7c9ffb9889c2de7743ff326f74a9b2ab8771

commit a49316f33d6066dd13d85f577dce84dd0278d4d0
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Wed Jun 29 13:43:02 2011 +0530

    mid_pmu:  do not issue set_command during s3 entry

    BZ: 4139

    during s3 entry dpm_suspend_noirq will call each of the drivers
    suspend calls and that in turn calls set_power_state() calls,
    we issue an interactive command to SCU and wait for the status
    interrupt this takes a long time until all the devices are suspended.
    This is not required since anyways after the devices are suspended
    we do S3 that puts all the devices in D0i3.

    We just cache the status of all the devices and configure that as
    the wakeup states after S3. This reduces the time to enter S3.

    Change-Id: Ice0f5b326335675890fa60ce6c546693d11d98f2
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 1df781ef9bbc9b0fc453537da2a3b1861f363138
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Thu Jun 23 04:58:43 2011 +0530

    mid_pmu:  sparse warnings fixed

    BZ: 3856

    Fixed the following sparse warnings.

    arch/x86/kernel/mid_pmu.c:302:18: warning: symbol 'pmu_wake_lock' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:1126:15: warning: symbol 'pmu_get_cstate' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:1813:3: warning: symbol 'medfield_lsses' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:1874:5: warning: symbol 'medfield_lsses_num' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:1876:6: warning: symbol 'lss_device_status' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:2368:5: warning: symbol 'mid_suspend' was not declared. Should it be static?

    fixed make namespacecheck issues.

    Change-Id: I7731a0391b1433a7ecfa28bdd3265591d1389495
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit c68b6b1636a4b898773a05a5651839806dd3314c
Author: Laurent Kappel <laurentx.kappel@intel.com>
Date:   Wed Jul 6 20:22:10 2011 +0200

    Revert "mid_pmu:  s0i1 lpmp3 s0i3 s3 automatic selection"

    This reverts commit e899b6438b842047bef1bbdfdf9188bd09fab447.

    Change-Id: I7d51be7532056ff81d89ce0bc2af8480ffc812ea
    Signed-off-by: Laurent Kappel <laurentx.kappel@intel.com>
commit e899b6438b842047bef1bbdfdf9188bd09fab447
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Fri Jun 17 10:13:31 2011 +0530

    mid_pmu:  s0i1 lpmp3 s0i3 s3 automatic selection

    BZ: 2457

    Automatically select s0i1, lpmp3, s0i3 or S3 does'nt happen currently,
    it is based on "echo s0i1/3 > /sys/modules/mid_pmu/parameters/s0ix"

    changed this to automatically select s0ix/lpmp3/s3 based on cpuidle
    latency and wakelocks.

    Change-Id: I5f3eef919aaac90d44e0d6ef0502c86f38da3ba2
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 54f32f953f356027c774c3cf46462992eadc73a7
Author: Pierre Tardy <pierre.tardy@intel.com>
Date:   Tue Jun 28 10:51:29 2011 +0200

    REVERTME:mid_pmu: deactivate S3 on PR2

    BZ: 4177

    quite a lot of patches are pending to enable S3 on PR2.
    Waiting for that we disable S3 by default on PR2

    to be reverted as soon as PR2 drivers are S3 capable

    Change-Id: I4de53e978fe850303617f8ace4ab9f073ce64d89
    Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit 5e73c57d106f8c766a5a06221e2817a7c9a5b393
Author: Rajesh Poornachandran <rajesh.poornachandran@intel.com>
Date:   Thu Jun 16 16:59:39 2011 -0700

    Revert "Revert "mid_pmu: Moving NC power management logic to OSPM""

    BZ: 1957

    Currently the PM for north complex was done independently by Gfx and ISP drivers.
    There was no synchronization between ISP and Gfx while sending the PM cmd.

    OSPM patch to provide an API, pmu_nc_set_power_state. This API will take care
    of talking to P-unit and getting the corresponding power islands to ON/OFF.
    Gfx and ISP drivers need to use this API in their drivers.

    Change-Id: I628dd8b03f5d09607e3c931e29943fcdb73613cb
    Signed-off-by: Sujith Thomas <sujith.thomas@intel.com>
    Signed-off-by: Rajesh Poornachandran <rajesh.poornachandran@intel.com>
commit 3b40317a7924fd4277b06992ea8755fe4d39094f
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Wed Jun 22 03:58:51 2011 +0530

    mid_pmu:  camera blocks s0ix when camera driver not present

    BZ: 3762

    With Camera driver removed we are not able to enter s0i1/3 S3, this is because
    the camera_off variable will be '0' even if the driver is not configured.

    conditionally set the variable '1' if camera device is not configured.

    Change-Id: Ia582399c8f3f493255e387a1a8ec0612fc6b50d0
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit dd6db50f98b6c0d368b9315124b65ec3b1aae2a1
Author: Erwan Mahe <erwanx.mahe@intel.com>
Date:   Thu Jun 23 18:29:21 2011 +0200

    Revert "Revert "mid_pmu: pick correct D0ix states in choose_state""

    BZ: 2102
    This reverts commit 41ff42ea4b74c89d7ed44b51e46ab7ae45b4b87c.

    Change-Id: I5aa5658cf28696a3c79a939ea8644a3b3c4d73f0

commit 41ff42ea4b74c89d7ed44b51e46ab7ae45b4b87c
Author: Marie-Celine Dubut <marie.celinex.dubut@intel.com>
Date:   Wed Jun 22 12:44:06 2011 +0200

    Revert "mid_pmu: pick correct D0ix states in choose_state"

    BZ 2102
    This reverts commit c60a2ae1f8b33abdabbff9c0de5a57ec6588df9d.

    Change-Id: I7e7aed5071adabc824c303628ba855031892e70a

commit c60a2ae1f8b33abdabbff9c0de5a57ec6588df9d
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Wed Jun 1 13:19:54 2011 +0530

    mid_pmu: pick correct D0ix states in choose_state

    BZ: 2102

    currently pmu_pci_choose_state return PCI_D3hot for all devices.
    For some of devices, it may not be possible to support PCI_D3hot state.
    eg., HSU needs to be put in D0i1, chaabi needs to be put in
    D0i2. It is not appropriate to always choose D0i3 for all devices

    We choose the correct state that is appropriate for each device
    for the  platform.

    This patch should be used only with a FW that is capable of supporting
    Chaabi D0i2.

    Change-Id: Ief7b64bc1ec37d4452ce3222454bdd6102d54c10
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit c4e73f14acb7ffd39a5d965fc23b1f01673363b8
Author: Hari Kanigeri <hari.k.kanigeri@intel.com>
Date:   Fri Jun 3 11:27:13 2011 -0600

    mid_pmu: fix checkpatch violations and some cleanup in exit paths

    BZ: 3066

    Fix the following:

    1. Checkpatch violations and cosmetic changes.
    2. fix correct cleanup in the exit paths of the function mid_pmu_probe

    Below log is related to checkpatch violations.

    1. Checkpatch violations
    =========================

    ERROR: space required before the open parenthesis '('
    +	if(pdev->device == 0x81c || pdev->device == 0x81b)

    WARNING: line over 80 characters
    +	for (i = 0; i < PMU_MAX_LSS_SHARE && intel_mid_pci_devices[index].dev_driver[i]; i++) {}

    ERROR: trailing statements should be on next line
    +	for (i = 0; i < PMU_MAX_LSS_SHARE && intel_mid_pci_devices[index].dev_driver[i]; i++) {}

    WARNING: braces {} are not necessary for single statement blocks
    +	for (i = 0; i < PMU_MAX_LSS_SHARE && intel_mid_pci_devices[index].dev_driver[i]; i++) {}

    WARNING: line over 80 characters
    +static pci_power_t  pmu_pci_get_weakest_state_for_lss(int lss_index, struct pci_dev *pdev, pci_power_t state)

    <cut here for brewity, please run checkpatch to see a complete list>

    total: 122 errors, 14 warnings, 2340 lines checked

    Change-Id: I1cdbd6a8b70d303611f0cd426ce63235010d0a07
    Signed-off-by: Hari Kanigeri <hari.k.kanigeri@intel.com>
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 3df93729faabfefb971badf3b51f8e652da3f288
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Mon Jun 13 01:52:20 2011 +0530

    mid_pmu: abort s0i3 c6offload write access not set

    BZ: 3356

    OSPM waits (busy loop) for "write access" to C6 Offload area to be granted by
    SCU. After sending S0ix command to SCU via the PM_CMD reg.

    In current OSPM code we clear "enable MSR" bit if we find c6 offload "write
    access" bit is not set, c6 offload wont happen, a c6 will still be issued. This
    will trigger ack_c6, but in this case SCU will check offload signature to
    makesure if offload has occurred, since it won't find the offload signature it
    should abort s0ix entry.

    We have busy loop'd considerable amount of time waiting for c6 "write
    access" bit to be set we may have overshot the c6 latency, hence it is better
    to demote the c6 to a c4.

    Change-Id: Ie0027ff4efb8a418a7377ba30eb6a20d0a74087c
    Signed-off-by: Illyas mansoor <illyas.mansoor@intel.com>
commit 4405feeea2eef28c40bda0e29817ee5ea223abe5
Author: MingmingX Zhang <mingmingx.zhang@intel.com>
Date:   Mon Jun 13 10:05:08 2011 +0800

    mid_pmu: delete repeated WARN in function mfld_s0i3_enter function

    BZ: 3346

    In function mfld_s0i3_enter, there are 2 WARN to check the same
    error status. Delete the needless WARN_ON.

    Change-Id: I8ba7cdab1eedf4bebdd3bfa599e3db795c56bdb0
    Signed-off-by: MingmingX Zhang <mingmingx.zhang@intel.com>
commit d332d4a59c01e1774cd4fdc28d97fe4d865989ee
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date:   Thu Feb 16 22:36:00 2006 +0530

    pmu: adding atomisp as part of entry criterion for S0i3

    BZ: 1339

    In current build we dont look at the isp runtime status before
    we enter S0i3 state. In this patch we check for the camera status
    in addition to all other device states that we check today in S0i3.

    Change-Id: If3f024fa22d0d744160b961e637e2b1c25e5e1c9
    Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
commit 397b53b9679edd28669876fbbb528a4f3a0daa7f
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Wed Jun 1 23:33:33 2011 +0530

    mid_pmu: adding s0ix first_entry time and residency

    BZ: 2709

    Earlier mid_pmu stats did'nt have first entry time and
    residency percentages. Also clear option was not available.

    Implemented the same.

    In order to clear pmu_stats please use the following command
    mount -t debugfs none /d
    echo "clear" > /d/mid_pmu_states

    Change-Id: I4f24272a11b017d0decdb875880e0bc27eb6bf18
    Signed-off-by: Sudharshan Ramachandra <sudarshan.n.ramachandra@intel.com>
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 71fd1c6ca28e68e7d3b8279a594bd51296e8be79
Author: Erwan Mahe <erwanx.mahe@intel.com>
Date:   Tue Jun 7 18:22:06 2011 +0200

    mid_pmu: s3/S0i3 automatic selection

    BZ: 2457

    Once the screen saver times out system would do few cycles of S0i3
    untill all the wakelocks are released then system will enter S3.This
    will avoid echo s0i1/3/x > /sys/module/mid_pmu/parameter/s0ix. This
    patch also increases the wakelock timeout for mid_pmu wakelock taken
    at end of s3 to 1 sec.

    Revert "Revert "mid_pmu: s3/S0i3 automatic selection""
    => Reinstate initial commit

    This reverts commit 21b136056afcfe32626a76ce2a3afe653a860c55.

    Change-Id: I19e2580bddc656c6ae809a6e1331bedc8579531b
    Signed-off-by: Erwan Mahe <erwanx.mahe@intel.com>
commit 21b136056afcfe32626a76ce2a3afe653a860c55
Author: Erwan Mahe <erwanx.mahe@intel.com>
Date:   Mon Jun 6 21:01:26 2011 +0200

    Revert "mid_pmu: s3/S0i3 automatic selection"

    This reverts commit c589050d2d9a90b0a6a334f57c9008c630fb24f1.

    Change-Id: I7e09f304b2eadffb27e83ab810c8a2edb8044fbd
    Signed-off-by: Erwan Mahe <erwanx.mahe@intel.com>
commit c589050d2d9a90b0a6a334f57c9008c630fb24f1
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date:   Mon Jun 6 10:38:11 2011 +0530

    mid_pmu: s3/S0i3 automatic selection

    BZ: 2457

    Once the screen saver times out system would do few cycles of S0i3
    untill all the wakelocks are released then system will enter S3.This
    will avoid echo s0i1/3/x > /sys/module/mid_pmu/parameter/s0ix. This
    patch also increases the wakelock timeout for mid_pmu wakelock taken
    at end of s3 to 1 sec.

    Change-Id: I5fc8e13ff0873d6dadd918ad8eabdaa0001e0950
    Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
commit 5e7997d26409e1e0f92c22c71b34fdcc4221e862
Author: Olivier Monnier <olivierx.monnier@intel.com>
Date:   Fri Jun 3 11:28:01 2011 +0200

    Revert "mid_pmu: s3/S0i3 automatic selection"

    This reverts commit f3ae17eb792bab5ab9bd5adcb0c5385cf9722c60.

    Change-Id: I2186fa8813677fcec6bf981c97aaf75dcff5ad5b
    Signed-off-by: Olivier Monnier <olivierx.monnier@intel.com>
commit f3ae17eb792bab5ab9bd5adcb0c5385cf9722c60
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date:   Thu May 26 15:48:28 2011 +0530

    mid_pmu: s3/S0i3 automatic selection

    BZ 2457

    Once the screen saver times out system would do few cycles of S0i3
    untill all the wakelocks are released then system will enter S3.This
    will avoid echo s0i1/3/x > /sys/module/mid_pmu/parameter/s0ix

    Change-Id: I7cb82c3bb519d769f1905632e7066985676bffef
    Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
commit 53f93b022da79eadc22a2ac5c3adade98380cf84
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Mon May 16 00:26:13 2011 +0530

    mid_pmu: demote c6 to c4 while s0ix is in progress

    BZ: 2120

    While S0ix aborts SCU waits for Ack_C6 timeout, IA comes out of
    mwait and since the SCU is still waiting for Ack_C6 the S0ix
    ACK_C6 timeout error interrupt is not recieved, meanwhile a new
    C6 could be triggered from IA and this could trigger a Ack_C6
    SCU can mistake this Ack_C6 as a ack for the previously aborted
    S0ix and continue S0ix flow. This is not correct.

    We check if the system is in S0ix progress state by checking
    scu_ready_sem if its already acquired that means S0ix is in
    progress and the subsequent C6 should be demoted to C4's

    Change-Id: I1b60824b28f9b6579dd551faa8fe485d2074b712
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 654da78fa8f45bcf4d64d9c0ea115d589f4374c4
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Sun May 15 23:44:23 2011 +0530

    mid_pmu: c6 offload msr bit cleanup

    BZ: 2116

    We were using magic number for wmsr(0x120) for setting/clearing
    offload bit.

    Fixed this by creating #defines

    Change-Id: I5fe4ec0568e48d12fe30074f8eebbc2a6411b4d8
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 516322a23d3e7b1606d83753b121de66e79daa20
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Mon May 16 11:09:48 2011 +0530

    mid_pmu: releasing scu_ready_sem in mfld_s3_enter

    BZ: 2179

    In function mfld_s3_enter we are checking if scu_ready_sem is already acquired.
    The intention is to make sure we enter S3 only if scu_ready_sem is free, but if
    its acquired instead of returning error we release the scu_ready_sem which is
    incorrect.

    removed the release of scu_ready_sem, if already acquired.

    Change-Id: I4ce888ae1702e4cdcb8dd584a87d0d10fb6c84db
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 8118849a0329d0e73761562443ae25c8b1cd3bf9
Author: Fengwei Yin <fengwei.yin@intel.com>
Date:   Sun May 22 11:57:12 2011 +0800

    Revert "mid_pmu:  Moving NC power management logic to OSPM"

    BZ: 2470

    This reverts commit 594c7f0327dd02985fbcde1e0bd83c98e684097f.

commit 594c7f0327dd02985fbcde1e0bd83c98e684097f
Author: Sujith Thomas <sthoma3@umg-lab1.iind.intel.com>
Date:   Thu May 12 10:51:38 2011 +0530

    mid_pmu:  Moving NC power management logic to OSPM

    BZ: 1957

    Currently the PM for north complex was done independently by Gfx and ISP drivers.
    There was no synchronization between ISP and Gfx while sending the PM cmd.

    OSPM patch to provide an API, pmu_nc_set_power_state.
    This API will take care of talking to P-unit and getting the corresponding power
    islands to ON/OFF. Gfx and ISP drivers need to use this API in their drivers.

    Change-Id: I302c9a7a6bb10ae572d340affb2502443d6178fc
    Signed-off-by: Sujith Thomas <sujith.thomas@intel.com>
commit abfc3b5f6d6df8a5d5985c73f99a8dc72cd18853
Author: Pierre Tardy <pierre.tardy@intel.com>
Date:   Mon May 16 16:49:50 2011 +0200

    Revert "Revert "Revert "REVERTME:mid_pmu: disable s0i3 by default for HSI IFWIs"""

    BZ: 2177

    This reverts commit eefaf8d45186b6ad465e67fb31cb4293c0a7a5fa.
    and re-enable s0i3 by default on HSI based IFWI

    Change-Id: Ib0289dcb5ef60b7750267aebb53f1bf38ab4ee3d
    Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit 50154e4edbe93d9d0d72e3b318cbe83b7e21831a
Author: Pierre Tardy <pierre.tardy@intel.com>
Date:   Mon May 16 13:32:44 2011 +0200

    mid_pmu: add more trace_printk

    BZ: 2139

    in order to see wake sources, and errors from s0i3 and s3

    Change-Id: If5d6ea297dde5d47ed79583c188d8457bb978076
    Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit 47f329c5a5a244636b7805b991d6ba5e1e8c7bd7
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date:   Mon May 16 09:29:28 2011 +0530

    pmu: fixing the aont mask fix for S3

    BZ 1756

    aont mask set for s3 was not proper which was not allowing to stay
    in S3. this patch fixes the mask.

    Change-Id: I8dc5a9372054d83a17184d289ea9ae7a621388bc
    Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
commit c52543cfc2fbade1fac03796c2b0615141e46cea
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Tue May 10 12:00:08 2011 +0530

    mid_pmu: fix incorrect residency for abort s0ix

    BZ: 1885

    In case of S0ix/Lpmp3 aborts for any reason we are still counting the
    residency times, in case of failure we should not account this time
    into actual s0ix/lpmp3 residency times.

    corrected this by only accumulating times for successful s0ix exits.

    Change-Id: Icdde3491fe786aec4c65795805bfec43d9c107f4
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit e0c7284d712fdc0715726ad1dc7df4ac6e9b18c9
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date:   Tue May 10 16:45:05 2011 +0530

    pmu: adding ignore wkc lss code needed for long s3

    BZ 1756

    This patch we add ignore wkc lss to add all those devices
    which needs to be ignored as wake sources during entry to s3
    state.

    Change-Id: I73a46d23f3bee2ef8d979162a4d1b6a020fe4bae
    Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
commit cba613f2bde66236706b9c0ba7f1fe6b5ff14ad7
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date:   Tue May 10 16:22:10 2011 +0530

    pmu:  renaming lss after new wkc implementation in scu

    BZ 1756

    This patch we are re assigning some of the lss to new lss
    based on the WKC implementation in scu.

    Change-Id: Ic7a9adf37194182b424dcdcc0d61cb09bba4a7a5
    Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
commit 43ea3ecf3ba252e6859f33d38d9c2bcd0e2c6f06
Author: Jean-Pierre Stierlin <jean-pierrex.stierlin@intel.com>
Date:   Fri Apr 29 11:01:35 2011 +0200

    mid_pmu: Disable S0i3 when HSI is not in D0i3

    BZ: 1226

    The platform should not enter S0i3 state when the HSI is still active

    Add PMU_HSI_LSS_03 to the s0ix_lss and lpmp3_lss tables

    Change-Id: I8ccddaa12d04b0af813820dad19fa96de7fe5e53
    Signed-off-by: Jean-Pierre Stierlin <jean-pierrex.stierlin@intel.com>
commit eefaf8d45186b6ad465e67fb31cb4293c0a7a5fa
Author: Erwan Mahe <erwanx.mahe@intel.com>
Date:   Thu May 5 12:12:04 2011 +0200

    Revert "Revert "REVERTME:mid_pmu: disable s0i3 by default for HSI IFWIs""

    This reverts commit a561e8620d08973fd5f9eea6a91488977fc3b539.

commit a561e8620d08973fd5f9eea6a91488977fc3b539
Author: Erwan Mahe <erwanx.mahe@intel.com>
Date:   Wed May 4 11:24:08 2011 +0200

    Revert "REVERTME:mid_pmu: disable s0i3 by default for HSI IFWIs"

    BZ: 1646

    This reverts commit 18a41ce2756933e6200e05283e3ea172c7aa320d.

commit d7a22f9c70e926ebe0bdb78a79153a5b8050a864
Author: Christophe Fiat <christophex.fiat@intel.com>
Date:   Thu Apr 28 14:55:45 2011 +0200

    mid_pmu: Add HSU in PMU Devices list blocking S0i3

    BZ: 932 - Taskforce: Mtfld-Android No Driver with D3/D0i3 for UART0

    Now that HSU is RT PM compliant, HSU can block s0i3 from happening when
    Bt active.

    put HSU LSS in the list of s0i3 and lpmp3 required lss.

    Change-Id: I0a4be909433b470b0b1dfa021fcc997d200cd835
    Signed-off-by: Christophe Fiat <christophex.fiat@intel.com>
    Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit 2f408985f4aeeb807ff095f0e86669fc6a6b14aa
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date:   Wed Apr 20 23:30:00 2011 +0530

    pmu: fixing wake sub system configuration on s3 exit

    wake sub system configuration was being set to D0 state
    on exit from S3. this is being reverted to state of devices
    before entering S3 to follow the same path as S0i3 flow.

    Change-Id: Ia6276b151b303912469511a5d1378e39b63d43b4
    Signed-off-by: Vishwesh M. Rudramuni <vishwesh.m.rudramuni@intel.com>
commit 96045de5b1e64969513c05f103d2db0d63c43b83
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Fri Apr 15 22:58:54 2011 +0530

    mid_pmu: change function name read_all_lss_states

    read_all_lss_states reads the current runtime_pm status of
    each SCU mapped pci driver and updates the current_status
    on to the corresponding LSS.

    The name leads to confusion since it implies reading of LSS
    regs which is not the case.

    Hence changing the name to update_all_lss_states

    Change-Id: I4f87b6e62f619db6ae07538a5a88ca70bf47c6aa
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 5d31bc498ade6f0ae46dad8298005724a0927ae2
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Thu Apr 14 00:05:28 2011 +0530

    [HSD:3743029] mid_pmu: hack: fix HSI lss not found in pci_table issue

    HSI drivers D0ix requested were not propogated to SCU
    on examination it was found that IA fw does not have
    the required driver to LSS mapping, hence the requests
    were skipped in PMU driver.

    Added a hack to fix this in PMU driver, revert this
    once IA FW fixes this issue.

    Change-Id: Iff5be2fa6a46dbd94dee787011b79ec347dcbaf3
    Signed-off-by: Illyas mansoor <illyas.mansoor@intel.com>
commit 18a41ce2756933e6200e05283e3ea172c7aa320d
Author: Pierre Tardy <pierre.tardy@intel.com>
Date:   Thu Apr 21 17:51:38 2011 +0200

    REVERTME:mid_pmu: disable s0i3 by default for HSI IFWIs

    HSI runtime_pm is not yet ready.
    device will go s0i3 even if there is HSI activity
    This causing lot of fabric errors.

    We disable s0i3 by default if we find HSI device (0x833)
    in the pci table.

    to be reverted as soon as HSI runtime_pm is ready.

    Change-Id: I9877c48ea78f0ea80528869ce978fb575385e621
    Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit 16a0bab0a9b9ae6cbcc4ec826315ef1d87cdc25d
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date:   Thu Apr 7 15:01:02 2011 +0530

    mid_pmu: enable full suspend to RAM (S3) (path#1)

    Enabling full suspend path in the pmu driver.

    use IRQF_NO_SUSPEND to keep irq alive during s3 path
    while we are at it removed unused irq parameter

    Changed the s0i3 wake lock in a timed wake lock for wakeup.
    This wakelocks stays locked until someone writes
    echo "s3s3" >/sys/modules/mid_pmu/parameters/s0ix
    So that system will still default to s0i3 until s3 is
    ready for everybody

    this patch also updates the s3 statistics.

    Change-Id: Ic496f3d96e70e9d37370413d9019e9a451d1b9c6
    Signed-off-by: Vishwesh M. Rudramuni <vishwesh.m.rudramuni@intel.com>
    Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit 1ec1299dd7c6854d9902640592003ec508f53bfc
Author: Pierre Tardy <pierre.tardy@intel.com>
Date:   Tue Apr 12 10:52:43 2011 +0200

    mid_pmu: add more powerfull s0ix statistics

    Current statistics only do s0ix entry count

    This adds timing statistics.
    This is mainly intended for automated tests, in order to make
    automated test have time spend in s0ix, and be able to do regressions
    over daily builds.

    There is also placeholder for s3 statistics that is not yet implemented.

    Change-Id: Ib2eed8e87f66c4efe8ca52767a76021576040333
    Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit bdb518ae8e9af2a27857cad22b6650b0bd20d9c8
Author: Pierre Tardy <pierre.tardy@intel.com>
Date:   Fri Apr 8 17:26:27 2011 +0200

    mid_pmu: suspend devices not in pci-table

    We suspend devices that are in the target config, and that are
    not in the pci table

    Some devices are indeed not advertised in pci
    table for certain firmwares. This is the case for HSI firmwares,
    SPI3 device is not advertised, and would then prevent s0i3.

    Change-Id: I319fcb8fe6ee3fa4a8272d2f2389aa4804a99699
    Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit 09bfcd007dd40dcead807525203baffe1371bb41
Author: Pierre Tardy <pierre.tardy@intel.com>
Date:   Wed Mar 2 18:35:03 2011 +0100

    mid_pmu/android: take a wakelock if s0i3 is not possible

    Change-Id: Icc3b1509873d76ad8afb63f04a8e52025c6c5c10

commit 3452915bdf4a946d0b969e646f00f2205a3b71b2
Author: Liu, ShuoX <shuox.liu@intel.com>
Date:   Tue Mar 15 11:37:26 2011 +0800

    modify s0ix default val for s0i3 debug

    Change-Id: I9ca88d1420768702b6550039d8313b61dafc5788

commit cfda66e44bc142f836c2e550211997759aa0d8e2
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Wed Mar 30 16:23:28 2011 +0530

    mid_pmu: cleanup added explicit LSS ids for s0ix entry

    Currently the LSS that need to be checked for S0ix/LPMP3
    entry is hardcoded making it difficult to read the sub
    system values.

    Added #defines for all the sub system LSS id's, using this
    defined the target config values to check against the SSS
    register values, that tells which subsystems need to in D0i3
    to issue S0i1/3 or LPMP3 commands.

    Also added a way to keep always ON LSS to be in D0i0.

    Added check for Keyboard, UART0/1/2 LSS in S0i1/lpmp3/S0i3 SSS
    config registers.

    Removed LSS 40, 41 from ignore_lss list.

    Change-Id: Ifd28b58f11c66232dc2993b3946c672bbe9931a3
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 4e082fe683a0d9b22b9ef0c6675705ba75a7dceb
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Wed Mar 30 16:22:21 2011 +0530

    mid_pmu: update current driver status during first interactive command

    At the time of pmu driver initialization we set all the LSS to be in D0i0
    state, this causes some of the drivers to be in forced D0i0 state in
    SCU, whereas there actual state could be D0i3, hence there could be
    potential power impact until next cycle of D0i0->D0i3 from the driver.

    To avoid this we acquire the lock, allow drivers to get blocked in
    pmu_pci_set_power_state(), then reflect the current driver state in
    SCU for all SCU managed drivers via setting the appropriate LSS values
    by issuing interactive command.

    This will ensure we reflect correct driver state during pmu driver
    initialization.

    Change-Id: I01caf76d6a32b38a556e7309457ab0e829b5dca4
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit a1e3d9fd3db6a395f9f45a233fc4a757e610700c
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Wed Mar 30 16:21:47 2011 +0530

    mid_pmu: added some counters

    Added counter to keep track of number of S0ix
    and error counts.

    Change-Id: I20d55781038a4732e50f98e0163eada394450702
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 37c03045efcd790183acdbd3cb94db59566bdb6d
Author: Pierre Tardy <pierre.tardy@intel.com>
Date:   Mon Mar 21 14:47:53 2011 +0100

    mid_pmu: allow several devices to be on the same lss

    HSU devices are in HW in the same lss.
    There is a workaround in IAFW, that will not advertise the correct lss
    for HSU0 and HSU1. This does not solve anything, as HSU0 driver will start
    to make fabric errors as soon as HSU2 is suspended.

    We generically solve the issue by maintaining a table of devices
    present in the same lss. For such very short list, we do not take the
    overhead of using linked list. but rather use a 4 slots table for each lss.

    This patch contains ss hardcode for HSU0 and HSU1. To be removed when
    IAFW remove the bad workaround.

    Change-Id: I11240c225edc92984cca7e5e176bbebab6df2d5d
    Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit aa7111008d6f823807dd117b4384ba66415eff40
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Fri Mar 18 12:10:59 2011 +0530

    mid_pmu: hack: replace lss 16 with 9

    IA FW is reporting Audio DMA subsytem id as 16, whereas it should report 9
    fixed this in the code, need to remove this once IA FW fixes this.

    Change-Id: I22b6bc9e425b43dae00233fd43b7bcf756c62c8b
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit feef0283493d0309bcf6c2021807e0150dc079d9
Author: Yanmin Zhang <yanmin.zhang@intel.com>
Date:   Tue Mar 8 16:18:49 2011 +0800

    Add a new interface under debugfs, pmu_sss_states, to output pmu sss registers. We could use it to check every subsystem state. mid_pmu_states saves device (subsystem) states intercepted by pci_set_power_state, while pmu_sss_states gets the states from pmu hardware registers.

    Change-Id: If0d9cb3b4286d1ea89064d9b94df29ed1ae2f7fa

commit fb7d10c9d7ba74245c1e14b739d207c920dab637
Author: mgross <mark.gross@intel.com>
Date:   Thu Mar 3 10:34:48 2011 +0800

    revert me asap block suspend to ram with wakelock

    Change-Id: I89812515397690f6dc99446a0f04c15bf2ac567e
    Signed-off-by: mgross <mark.gross@intel.com>
commit 0d15acc903de50173abffbc8e7830749e46c4ef6
Author: mgross <mark.gross@intel.com>
Date:   Mon Feb 28 15:18:46 2011 -0800

    Stub to enable pm_suspend and android early suspend calls to start
    working.
    With this change (and the propper config file) you can enter early
    suspend and start enabling android power managment.

    Change-Id: I80c10a33f8fc80221502761175ed372a379ae779

commit 0c2cb76662387a575c6f41b9f91a85cd76064f55
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Sat Feb 5 14:52:41 2011 +0100

    mid_pmu: cleanup: fix sparse check warnings

    moved all #defines to mid_pmu.h

    fixed warnings after installing sparse tool

    Fixed the following warnings from sparse.
    with make C=2 >& sparse.log command.

    arch/x86/kernel/mid_pmu.c:46:3: warning: symbol 'pci_dev_index' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:1175:70: warning: incorrect type in argument 2 (different address spaces)
    arch/x86/kernel/mid_pmu.c:1175:70:    expected void volatile [noderef] <asn:2>*addr
    arch/x86/kernel/mid_pmu.c:1175:70:    got unsigned int *
    arch/x86/kernel/mid_pmu.c:1180:76: warning: incorrect type in argument 2 (different address spaces)
    arch/x86/kernel/mid_pmu.c:1180:76:    expected void volatile [noderef] <asn:2>*addr
    arch/x86/kernel/mid_pmu.c:1180:76:    got unsigned int *
    arch/x86/kernel/mid_pmu.c:322:5: warning: symbol 'get_target_platform_state' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:691:6: warning: symbol 'mfld_s0i1_enter' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:717:5: warning: symbol 'mfld_s0i3_enter' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:844:5: warning: symbol 'is_msi_enabled' was not declared. Should it be static?
    arch/x86/kernel/mid_pmu.c:1191:59:    got unsigned int *
    arch/x86/kernel/mid_pmu.c:1502:13: warning: incorrect type in assignment (different address spaces)
    arch/x86/kernel/mid_pmu.c:1502:13:    expected struct mrst_pmu_reg *pmu
    arch/x86/kernel/mid_pmu.c:1502:13:    got void [noderef] <asn:2>*
    arch/x86/kernel/mid_pmu.c:1567:27:    expected void [noderef] <asn:2>*<noident>
    arch/x86/kernel/mid_pmu.c:1567:27:    got struct mrst_pmu_reg *static [toplevel] *<noident>
    ...
    and similar warnings.

    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit cf3aa8b17adab4006d49f01aa66bd184f9598eb8
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Fri Feb 4 01:12:34 2011 +0100

    mid_pmu: wait for interactive command complete in pmu_init

    At the time of pmu_init we set all the LSS's into D0i0 mode
    by sending an interactive command. This command was not
    waiting for interactive complete semaphore that is released
    from pmu interrupt handler.

    Also interrupt handler was registered after pmu_init, which
    should be the otherway.

    This will ensure the interrupt handler is registered before
    calling pmu_init and also after interactive command is sent
    in pmu_init() we wait for interactive command complete semaphore.

    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 9d8e0e6094afb88033a3e85cb92e905a8f87cb60
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Fri Feb 4 00:14:00 2011 +0100

    mid_pmu: wake source counter statistics

    We need a way to tell which logical subsystem woke up from S0i3
    Wake status register provides this information.

    We provide a way to capture how many times each LSS
    woke up the system from S0i3, by reading Wake status
    register and incrementing a counter for each LSS.

    This is printed as part of /sys/kernel/debug/mid_pmu_states

    Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
    Acked-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 54c94eb1ef0d810458a6d4b3b558a356fce54493
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Mon Jan 31 04:22:59 2011 +0100

    mid_pmu: clear cpu offload cntrl reg in error scenarios

    For S0i3 case we need to set the offload cntrl reg to copy the contents
    of IA C6 SRAM to SC always on SRAM. In case of error if S0i3 fails for
    some reason, or on S0ix successful completion this bit needs to be cleared.

    We ensure it's set during S0i3 entry and is cleared in interrupt handler.

    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 98cb52baaeb1c7d058ec3a12db943f7c60918605
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Fri Jan 28 05:37:37 2011 +0100

    mid_pmu: bug fix: change lpmp3 command value

    For LPMP3, trigger must be based on "core must be idle" (cmbi)
    and not just C6. Hence LPMP3 was breaking.

    After setting cmbi bit as the trigger, LPMP3 usecase works.

    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 4908f77de188bae7b61b39113747eef2f2bd9b83
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Fri Jan 28 05:36:18 2011 +0100

    mid_pmu: disable scu semaphore watchdog by default

    SCU semaphore watchdog is getting triggered with 500ms
    timeout value, because of which we see synchronization
    issues, providing an option to selectively enabling it.

    By default disabled.

    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 8e35a33d7754c82fb89e48d25ff3988e4cc03977
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Thu Jan 27 03:38:19 2011 +0100

    mid_pmu: bug fix: fixed device lss reporting lss0 wrongly

    The MSB of "logical subsystem" byte tells if the device is managed
    by SCU, the MSB was not being checked before getting the LSS
    values.

    This was causing drivers that were not part of SCU getting
    LSS value '0'

    By checking the MSB of "logical sub sytemid" byte from PCI config
    we will get to know if this driver actually belongs to SCU, and
    hence avoid multiple drivers with LSS value 0.

    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit 33d19d30ff22685f18f184183b1e675d8fe94fea
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date:   Mon Jan 17 08:22:32 2011 +0100

    mid_pmu: driver that controls pmus of intel_mid platforms

    Mobile Internet Devices based on the Intel "Medfield" platform have two
    Platform Management Units (PMU). The first PMU (pmu1) comprises of the
    Silverthorne CPU, Graphics, Video encode/decode and Display engines,
    The second PMU (pmu2) is the IO hub.

    The Platform Management Unit (PMU) driver is a Medfield-specific power
    management driver. Intel's  MID provides fine tuned knobs for
    platform level. Intel's Medfield MID provides control for platform
    level power management and the OS Power Management solution guides the
    power states that the subsystems and CPU needs to be in depending on the
    current usage and power policy set by the user.

    The purpose of the Medfield Power Management architecture is to turn
    off subsystems without affecting the end user functionality/usability of
    the system.

    The Power Management scheme uses the concept of operating modes, which
    define the configuration of all the subsystems under each of the usage model
    that the user might put the system in. Based on current platform usage,
    OSPM decides the target power states for the sub systems, and the PMU
    driver implements the OS-HW interface.

    "Intel" Medfield PMU driver interfaces with two power management units
    (PMU) pmu1 & pmu2. On receiving commands PMU driver interfaces
    with the pmu1 & pmu2 via a well defined register interface to drive the
    required power  management flows.

    This patch contains:
    - key definitions for the PMU driver.
    - core logic of the PMU driver as it interfaces with pmu1 & pmu2 for
    different platform power management flows.

    Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
    Signed-off-by: Rajeev D Muralidhar <rajeev.d.muralidhar@intel.com>
    Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>