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(parent: 9ad565f) | patch
[ARM][LowOverheadLoops] Add CPSR defs
authorSam Parker <sam.parker@arm.com>
Fri, 26 Jul 2019 08:15:01 +0000 (08:15 +0000)
committerSam Parker <sam.parker@arm.com>
Fri, 26 Jul 2019 08:15:01 +0000 (08:15 +0000)
commitc760b5da11648acf0e8191069e72188e88b5524a
tree6437830518275bca1d3b1e75f7a3c0a0927c43f7tree | snapshot
parent9ad565f70ec5fd3531056d7c939302d4ea970c83commit | diff
[ARM][LowOverheadLoops] Add CPSR defs

Both WhileLoopStart and LoopEnd may get turned into a cmp and br pair,
so add an implicit def to these pseudo instructions in case that WLS
and LE aren't generated.

Differential Revision: https://reviews.llvm.org/D65275

llvm-svn: 367089
13 files changed:
llvm/lib/Target/ARM/ARMInstrThumb2.td diff | blob | history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir diff | blob | history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir diff | blob | history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir diff | blob | history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir diff | blob | history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir diff | blob | history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir diff | blob | history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir diff | blob | history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir diff | blob | history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir diff | blob | history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir diff | blob | history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir diff | blob | history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir diff | blob | history
Domain: System / Toolchain;