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[RISCV] Add test cases miscompile of (rotl (grevi X, 24), 16) on RV64. NFC
authorCraig Topper <craig.topper@sifive.com>
Mon, 28 Feb 2022 20:59:48 +0000 (12:59 -0800)
committerCraig Topper <craig.topper@sifive.com>
Tue, 1 Mar 2022 15:32:07 +0000 (07:32 -0800)
commitc752eb4ae19710983500eef963e258b207e42df0
tree13cc41417e5f1406d3c22b8c74c5027f7b2799f3tree | snapshot
parenta1f442b2787ef63ba84c8627987cfebe3ba4f7f6commit | diff
[RISCV] Add test cases miscompile of (rotl (grevi X, 24), 16) on RV64. NFC

This pattern was moved from isel to DAG combine in D119527, but
it lost the RV32 qualification in the process.
llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll diff | blob | history
Domain: System / Toolchain;