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(parent: c04b530) | patch
[X86] Replace more calls to getZeroVector with regular getConstant.
authorCraig Topper <craig.topper@intel.com>
Tue, 20 Nov 2018 06:54:01 +0000 (06:54 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 20 Nov 2018 06:54:01 +0000 (06:54 +0000)
commitc733c7bf94f8eecbe8de9e36d0c8f0c078530cba
treeaf77376d5d43abb8a2cea930a7727d8d03ae0eadtree | snapshot
parentc04b5307d17a80d4e628ec97a5ea706d205307b7commit | diff
[X86] Replace more calls to getZeroVector with regular getConstant.

getZeroVector produces a specifically canonicalized zero vector, but we can just let DAG legalization take care of it.

The test changes are because MULH lowering happens later than it should and this change gave us the opportunity to constant fold away a multiply during a DAG combine before the build_vector got legalized with a bitcast.

llvm-svn: 347290
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/X86/combine-sdiv.ll diff | blob | history
Domain: System / Toolchain;