i965: Introduce a "memory zone" concept on BO allocation.
authorKenneth Graunke <kenneth@whitecape.org>
Mon, 9 Apr 2018 23:47:11 +0000 (16:47 -0700)
committerKenneth Graunke <kenneth@whitecape.org>
Tue, 22 May 2018 17:01:09 +0000 (10:01 -0700)
commitc7259259d4c0df9ba339f4927891c855c7f91924
treed830b6058d5fb8b74284ed22ac9aa47e1715c439
parent417b9e5770436008a7f00cfaffe9ddf4c5a13502
i965: Introduce a "memory zone" concept on BO allocation.

We're planning to start managing the PPGTT in userspace in the near
future, rather than relying on the kernel to assign addresses.  While
most buffers can go anywhere, some need to be restricted to within 4GB
of a base address.

This commit adds a "memory zone" parameter to the BO allocation
functions, which lets the caller specify which base address the BO will
be associated with, or BRW_MEMZONE_OTHER for the full 48-bit VMA.

Eventually, I hope to create a 4GB memory zone corresponding to each
state base address.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
16 files changed:
src/mesa/drivers/dri/i965/brw_blorp.c
src/mesa/drivers/dri/i965/brw_bufmgr.c
src/mesa/drivers/dri/i965/brw_bufmgr.h
src/mesa/drivers/dri/i965/brw_context.h
src/mesa/drivers/dri/i965/brw_performance_query.c
src/mesa/drivers/dri/i965/brw_pipe_control.c
src/mesa/drivers/dri/i965/brw_program.c
src/mesa/drivers/dri/i965/brw_program_cache.c
src/mesa/drivers/dri/i965/brw_queryobj.c
src/mesa/drivers/dri/i965/gen6_queryobj.c
src/mesa/drivers/dri/i965/gen6_sol.c
src/mesa/drivers/dri/i965/intel_batchbuffer.c
src/mesa/drivers/dri/i965/intel_buffer_objects.c
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
src/mesa/drivers/dri/i965/intel_screen.c
src/mesa/drivers/dri/i965/intel_upload.c