clk: samsung: clk-pll: Add support for pll1417x
authorDavid Virag <virag.david003@gmail.com>
Mon, 6 Dec 2021 15:31:19 +0000 (16:31 +0100)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Sun, 19 Dec 2021 22:39:01 +0000 (23:39 +0100)
commitc703a2f44cce4693c8d974ed1f583143261d81c1
tree9dfe8a1d2927879d814308829c4b56d0f41db550
parentcfe238e4e7ff1701b010a5ff7c64ae11d53ed8cb
clk: samsung: clk-pll: Add support for pll1417x

pll1417x is used in Exynos7885 SoC for top-level integer PLLs.
It is similar enough to pll0822x that practically the same code can
handle both. The difference that's to be noted is that when defining a
pl1417x PLL, the "con" parameter of the PLL macro should be set to the
CON1 register instead of CON3, like this:

    PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
        PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
        NULL),

Signed-off-by: David Virag <virag.david003@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20211206153124.427102-6-virag.david003@gmail.com
drivers/clk/samsung/clk-pll.c
drivers/clk/samsung/clk-pll.h