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intel_gtt: Properly support gen6+ GTT PTEs
authorBen Widawsky <benjamin.widawsky@intel.com>
Sun, 1 Sep 2013 19:17:23 +0000 (12:17 -0700)
committerBen Widawsky <benjamin.widawsky@intel.com>
Tue, 3 Sep 2013 22:31:14 +0000 (15:31 -0700)
commitc6f9bdc66f9ed82c82c1e77bb8bbadc250648c6e
tree153b6b55f0699b664ef910c16d3fa7f38414eac7tree | snapshot
parent8adfb5886dd1128fc8c8c70c79fffbc62b0a7975commit | diff
intel_gtt: Properly support gen6+ GTT PTEs

This finishes the objective in the last patch which was to actually deal
with physical addresses, and not the PTEs.

GEN6+ Provided support for physical addresses above 4GB. I'm not
actually sure what Ironlake supported, and don't feel like firing up the
timemachine.

v2: Add support for gen4, gen5, and haswell.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
tools/intel_gtt.c diff | blob | history
Domain: SCM / Uncategorized;