[AArch64] More consistently use buildvector for zero and all-ones constants
authorDavid Green <david.green@arm.com>
Mon, 20 Feb 2023 14:13:53 +0000 (14:13 +0000)
committerDavid Green <david.green@arm.com>
Mon, 20 Feb 2023 14:13:53 +0000 (14:13 +0000)
commitc6c6723189f40b0ea823925bd616ff1bdb0eccf3
treeb8387749352d5232e05866dc2115112c4f8a8c43
parentc21ccebe6f5293fc1359456b31d188edc9c5ac66
[AArch64] More consistently use buildvector for zero and all-ones constants

The AArch64 backend will use legal BUILDVECTORs for zero vectors or all-ones
vectors, so during selection tablegen patterns get rely on immAllZerosV and
immAllOnesV pattern frags in patterns like vnot. It was not always consistent
though, which this patch attempt to fix by recognizing where constant splat +
insert vector element is used. The main outcome of this will be that full
vector movi v0.2d, #0000000000000000 will be used as opposed to movi d0, #0, as
per https://reviews.llvm.org/D53579. This helps simplify what tablegen will
see, to make pattern matching simpler.

Differential Revision: https://reviews.llvm.org/D144018
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/build-one-lane.ll
llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll
llvm/test/CodeGen/AArch64/urem-vector-lkk.ll
llvm/test/CodeGen/AArch64/vecreduce-add-legalization.ll
llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll