drm/i915: Prepare link training for per-lane drive settings
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 1 Oct 2021 13:01:06 +0000 (16:01 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 4 Oct 2021 10:04:36 +0000 (13:04 +0300)
commitc6921d484d3f986f3bed3372ac22574b42e2589f
tree4210f3fdc4d42fb16e616291945d48de7a6c25f9
parentd0920a45574c15a8fc00ccdff65da3b801438757
drm/i915: Prepare link training for per-lane drive settings

Adjust the link training code to accommodate per-lane drive settings,
if supported by the platform. Actually enabling this will involve
some changes to each platform's .set_signal_level() implementation,
so for the moment all supported platforms will keep using the current
codepath that just uses the same drive settings for all the lanes.

v2: Fix min() vs. max() fumble
v3: Compact the debug print to a single line

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211001130107.1746-10-ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/display/intel_dp_link_training.c