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(parent: 0bde5e4) | patch
[RISCV] Remove EEW from some sched classes.
authorCraig Topper <craig.topper@sifive.com>
Thu, 20 Oct 2022 15:13:25 +0000 (08:13 -0700)
committerCraig Topper <craig.topper@sifive.com>
Thu, 20 Oct 2022 15:23:22 +0000 (08:23 -0700)
commitc66426f3a06fa8626b1bd4fb0844aa04a424037c
tree0a9a4caa2f7e779cd22fbaa35f519668c5a42337tree | snapshot
parent0bde5e4bec3927a58b2bda215ed0f5cce8166f4bcommit | diff
[RISCV] Remove EEW from some sched classes.

This removes the EEW from unit stride load/store and whole register
load, store, move.

It seems reasonable that implementations of these instructions wouldn't
usually be affected by element width.

We likely need to add LMUL information to our scheduling classes so
I thought it might be good to remove a few before they got multiplied
by LMUL.

Reviewed By: reames, michaelmaitland

Differential Revision: https://reviews.llvm.org/D135992
llvm/lib/Target/RISCV/RISCVInstrInfoV.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td diff | blob | history
llvm/lib/Target/RISCV/RISCVScheduleV.td diff | blob | history
Domain: System / Toolchain;