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(parent: a506f5b) | patch
[NVPTX] Implement custom lowering of loads/stores for i1
authorJustin Holewinski <jholewinski@nvidia.com>
Wed, 14 Nov 2012 19:19:16 +0000 (19:19 +0000)
committerJustin Holewinski <jholewinski@nvidia.com>
Wed, 14 Nov 2012 19:19:16 +0000 (19:19 +0000)
commitc6462aacd58021f4f9c38d2d196dcbe80d68302e
tree08d47bde9a1b3bbdbbbf10d29dcf587f3039bccdtree | snapshot
parenta506f5b0fd2ece7f6ba69c3bf0f4b774a1fed8adcommit | diff
[NVPTX] Implement custom lowering of loads/stores for i1

Loads from i1 become loads from i8 followed by trunc
Stores to i1 become zext to i8 followed by store to i8

Fixes PR13291

llvm-svn: 167948
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp diff | blob | history
llvm/lib/Target/NVPTX/NVPTXISelLowering.h diff | blob | history
llvm/test/CodeGen/NVPTX/pr13291-i1-store.ll [new file with mode: 0644] blob
Domain: System / Toolchain;