powerpc/mpc8xxx: Add memory reset control
authorYork Sun <yorksun@freescale.com>
Tue, 25 Jun 2013 18:37:48 +0000 (11:37 -0700)
committerYork Sun <yorksun@freescale.com>
Fri, 9 Aug 2013 19:41:39 +0000 (12:41 -0700)
commitc63e137014cf148bc1d234128941dccee3d519ae
treeafb69c22c33459d14a174973083e2a70e5f49ea7
parentb61e06156660579ea6e248abd2506ebdd85e7a14
powerpc/mpc8xxx: Add memory reset control

JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.

Signed-off-by: York Sun <yorksun@freescale.com>
16 files changed:
arch/powerpc/cpu/mpc85xx/ddr-gen1.c
arch/powerpc/cpu/mpc85xx/ddr-gen2.c
arch/powerpc/cpu/mpc85xx/ddr-gen3.c
arch/powerpc/cpu/mpc86xx/ddr-8641.c
arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
arch/powerpc/cpu/mpc8xxx/ddr/main.c
arch/powerpc/include/asm/fsl_ddr_sdram.h
board/freescale/bsc9131rdb/ddr.c
board/freescale/bsc9132qds/ddr.c
board/freescale/common/qixis.c
board/freescale/corenet_ds/ddr.c
board/freescale/p1010rdb/ddr.c
board/freescale/p1_p2_rdb/ddr.c
board/freescale/p1_p2_rdb_pc/ddr.c
board/freescale/p1_twr/ddr.c
include/configs/T4240QDS.h