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(parent: 9dc6ce8) | patch
RISC-V: Add CSR encodings for all HPMCOUNTERS
authorAtish Patra <atish.patra@wdc.com>
Sat, 19 Feb 2022 00:46:53 +0000 (16:46 -0800)
committerPalmer Dabbelt <palmer@rivosinc.com>
Mon, 21 Mar 2022 21:58:16 +0000 (14:58 -0700)
commitc631121dd16ee57ceb0d6a48e1357382b98350fd
treef01a6d3d86b20261ada750b1c46424e30ec788eftree | snapshot
parent9dc6ce80213635cdca611d8b89f74bf010c1a8c6commit | diff
RISC-V: Add CSR encodings for all HPMCOUNTERS

Linux kernel can directly read these counters as the HPMCOUNTERS CSRs are
accessible in S-mode.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/csr.h diff | blob | history
Domain: System / Kernel;