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[VP][SelectionDAG][RISCV] Add get_vector_length intrinsics and generic SelectionDAG...
authorCraig Topper <craig.topper@sifive.com>
Fri, 26 May 2023 16:01:28 +0000 (09:01 -0700)
committerCraig Topper <craig.topper@sifive.com>
Fri, 26 May 2023 16:06:38 +0000 (09:06 -0700)
commitc5e6c886aabb36ab66b4ed835da243c2a3455ade
treeb60da4c9c196b204ae89af3b34e77a2e04fa6e08tree | snapshot
parentbfb1ba752655bf09b35c486f6cc9817dbedfb1bbcommit | diff
[VP][SelectionDAG][RISCV] Add get_vector_length intrinsics and generic SelectionDAG support.

The generic implementation is umin(TC, VF * vscale).

Lowering to vsetvli for RISC-V will come in a future patch.

This patch is a pre-requisite to be able to CodeGen vectorized code from
D99750.

Reviewed By: reames, frasercrmck

Differential Revision: https://reviews.llvm.org/D149916
llvm/docs/LangRef.rst diff | blob | history
llvm/include/llvm/CodeGen/SelectionDAG.h diff | blob | history
llvm/include/llvm/CodeGen/TargetLowering.h diff | blob | history
llvm/include/llvm/IR/Intrinsics.td diff | blob | history
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff | blob | history
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp diff | blob | history
llvm/lib/IR/Verifier.cpp diff | blob | history
llvm/test/CodeGen/AArch64/get_vector_length.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll [new file with mode: 0644] blob
llvm/test/Verifier/get_vector_length.ll [new file with mode: 0644] blob
Domain: System / Toolchain;