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(parent: d49dc88) | patch
phy: rockchip: naneng-combphy: Support rk3588
authorJon Lin <jon.lin@rock-chips.com>
Thu, 27 Apr 2023 07:35:35 +0000 (10:35 +0300)
committerKever Yang <kever.yang@rock-chips.com>
Wed, 17 May 2023 09:36:18 +0000 (17:36 +0800)
commitc5b4a012bca8e584615163ee1058d0f92ce94a26
tree778f87f705a37310e4fbf902e007cc9b30c9d703tree | snapshot
parentd49dc884cb8e02b8640a5059a5e54facd80fe679commit | diff
phy: rockchip: naneng-combphy: Support rk3588

Add support for rk3588 phy variant.
The PHY clock is fixed at 100MHz.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
[kever.yang@rock-chips.com: update pcie pll parameters]
Co-developed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[eugen.hristev@collabora.com: squashed, tidy up]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c diff | blob | history
Domain: System / Kernel;