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(parent: b1e9b87) | patch
tools/power/x86/intel-speed-select: Hide invalid TRL level
authorZhang Rui <rui.zhang@intel.com>
Thu, 18 Aug 2022 13:21:46 +0000 (21:21 +0800)
committerSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Wed, 22 Mar 2023 20:36:55 +0000 (13:36 -0700)
commitc5a295caefa33ce7599d7afbe7a2e9b1bc8d92a2
tree1719bcf36c07728b8d6fe811ae922a1a2ef08881tree | snapshot
parentb1e9b87b3b5999786685eb882afb99c468af94c1commit | diff
tools/power/x86/intel-speed-select: Hide invalid TRL level

TRL levels with Zero ratio values is meaningless.
Prevent these TRL levels from being displayed.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
tools/power/x86/intel-speed-select/isst-display.c diff | blob | history
Domain: System / Kernel;