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[AArch64] Avoid partial register writes on lane 0 of BUILD_VECTOR for i8/i16/f16
authorAdam Nemet <anemet@apple.com>
Thu, 13 Apr 2017 23:32:47 +0000 (23:32 +0000)
committerAdam Nemet <anemet@apple.com>
Thu, 13 Apr 2017 23:32:47 +0000 (23:32 +0000)
commitc5779460f4cbea38dc77911b667a6d76c79c1a3f
tree9c3ea8a5a6c33e1ec0958d92123acec18de886d5tree | snapshot
parentd24aeb20fc3ac57a2180380edbeb3c0fa0cd03b2commit | diff
[AArch64] Avoid partial register writes on lane 0 of BUILD_VECTOR for i8/i16/f16

This further improves Ahmed's change in rL299482.  See the new comment for the
rationale.

The patch recovers most of the regression for bzip2 after D31965. We're down
to +2.68% from +6.97%.

Differential Revision: https://reviews.llvm.org/D32028

llvm-svn: 300276
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll diff | blob | history
llvm/test/CodeGen/AArch64/arm64-neon-copy.ll diff | blob | history
llvm/test/CodeGen/AArch64/concat_vector-scalar-combine.ll diff | blob | history
Domain: System / Toolchain;