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[RISCV] Split f64 undef into two i32 undefs
authorwangpc <pc.wang@linux.alibaba.com>
Tue, 8 Feb 2022 05:42:15 +0000 (13:42 +0800)
committerwangpc <pc.wang@linux.alibaba.com>
Tue, 8 Feb 2022 05:42:15 +0000 (13:42 +0800)
commitc53d99c37de5028beca32416727e609d2dffacba
tree3cf6427a824d3ec9d71529776d0c48e7a84895c4tree | snapshot
parentadbc7a2665768d54a7b35e8d9e5d4a02dee6de6dcommit | diff
[RISCV] Split f64 undef into two i32 undefs

So that no store instruction will be generated.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D118222
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/test/CodeGen/RISCV/double-calling-conv.ll diff | blob | history
Domain: System / Toolchain;