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(parent: 80c0077) | patch
i965: Add register coalescing to the new FS backend.
authorEric Anholt <eric@anholt.net>
Tue, 5 Oct 2010 17:29:42 +0000 (10:29 -0700)
committerEric Anholt <eric@anholt.net>
Fri, 8 Oct 2010 20:22:27 +0000 (13:22 -0700)
commitc52a0b5c7d4b55fb183c8ab68aa3561432287283
tree3e6ce808400ca97bd9c66cc8303d10a8fdb2f130tree | snapshot
parent80c0077a6f7908b302e9fd03ab0d2e5c30dcbdddcommit | diff
i965: Add register coalescing to the new FS backend.

Improves performance of my GLSL demo 14.3% (+/- 4%, n=4) by
eliminating the moves used in ir_assignment and ir_swizzle handling.
Still 16.5% to go to catch up to the Mesa IR backend, presumably
because instructions are almost perfectly mis-scheduled now.
src/mesa/drivers/dri/i965/brw_fs.cpp diff | blob | history
Domain: Graphics System / GL;