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(parent: d3319d1) | patch
ACPICA: Fix writes to optional PM1B registers
authorBob Moore <robert.moore@intel.com>
Wed, 18 Feb 2009 06:20:12 +0000 (14:20 +0800)
committerLen Brown <len.brown@intel.com>
Thu, 26 Mar 2009 20:38:24 +0000 (16:38 -0400)
commitc520abadbc56a2740021910d2c6412f826a10059
treebb491ead1a13afcf759d42e29175c5391449661ctree | snapshot
parentd3319d1717a250e92be66a487dc3e0429112c284commit | diff
ACPICA: Fix writes to optional PM1B registers

On read, shift B register bits above the A bits. On write,
shift B bits down to zero before writing the B register. New:
acpi_hw_read_multiple, acpi_hw_write_multiple. These two functions now
transparently handle the (possible) split registers for PM1 Status,
Enable, and Control.

Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
drivers/acpi/acpica/hwregs.c diff | blob | history
Domain: System / Uncategorized;