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(parent: 45ad6fa) | patch
[RISCV] Make the code in MatchSLLIUW ignore the lower bits of the AND mask where...
authorCraig Topper <craig.topper@sifive.com>
Sun, 24 Jan 2021 08:13:12 +0000 (00:13 -0800)
committerCraig Topper <craig.topper@sifive.com>
Sun, 24 Jan 2021 08:34:45 +0000 (00:34 -0800)
commitc50457f3e4209b0cd0d4a6baa881bac30a9d3016
treea9310d07e351d4536239d22e69863ded37d01949tree | snapshot
parent45ad6fac6ad0dea2a1f7a1c6b65b64d230757667commit | diff
[RISCV] Make the code in MatchSLLIUW ignore the lower bits of the AND mask where the shift has guaranteed zeros.

This avoids being dependent on SimplifyDemandedBits having cleared
those bits.

It could make sense to teach SimplifyDemandedBits to keep all
lower bits 1 in an AND mask when possible. This could be
implemented with slli+srli in the general case rather than
needing to materialize the constant.
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp diff | blob | history
Domain: System / Toolchain;