[CodeGen][ShrinkWrap] Enable PostShrinkWrap by default
authorsgokhale <sgokhale@nvidia.com>
Thu, 25 May 2023 08:24:47 +0000 (13:54 +0530)
committersgokhale <sgokhale@nvidia.com>
Thu, 25 May 2023 08:26:29 +0000 (13:56 +0530)
commitc4a60c9d34375e73fc2da5e02215eabe4bc90e8f
tree53ebce3d284f81246bc565ca4cab80ad977152c5
parent20d6dee40d507d467d3312d5e7dfdf088f106d31
[CodeGen][ShrinkWrap] Enable PostShrinkWrap by default

This is an attempt to reland D42600 and enabling this optimisation by default.

This also resolves the issue pointed out in the context of PGO build.

Differential Revision: https://reviews.llvm.org/D42600
39 files changed:
llvm/lib/CodeGen/ShrinkWrap.cpp
llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
llvm/test/CodeGen/AArch64/ragreedy-csr.ll
llvm/test/CodeGen/AArch64/shrinkwrap-split-restore-point.mir [new file with mode: 0644]
llvm/test/CodeGen/AArch64/taildup-cfi.ll
llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
llvm/test/CodeGen/ARM/code-placement.ll
llvm/test/CodeGen/ARM/mbp.ll
llvm/test/CodeGen/ARM/ssat-unroll-loops.ll
llvm/test/CodeGen/PowerPC/common-chain-aix32.ll
llvm/test/CodeGen/PowerPC/common-chain.ll
llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
llvm/test/CodeGen/PowerPC/lsr-profitable-chain.ll
llvm/test/CodeGen/PowerPC/shrink-wrap.ll
llvm/test/CodeGen/PowerPC/shrink-wrap.mir
llvm/test/CodeGen/RISCV/aext-to-sext.ll
llvm/test/CodeGen/RISCV/fli-licm.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/inlineasm.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/sibling-loops.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
llvm/test/CodeGen/Thumb2/mve-gather-tailpred.ll
llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll
llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
llvm/test/CodeGen/Thumb2/mve-scatter-increment.ll
llvm/test/CodeGen/Thumb2/mve-tailpred-nonzerostart.ll
llvm/test/CodeGen/Thumb2/mve-vmull-loop.ll
llvm/test/CodeGen/X86/fold-call-3.ll
llvm/test/CodeGen/X86/negative-stride-fptosi-user.ll
llvm/test/CodeGen/X86/pr44412.ll
llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
llvm/test/Transforms/LoopStrengthReduce/AArch64/pr53625.ll
llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll