MIPS: First MIPS R6 architecture implementation

MIPS: First MIPS R6 architecture implementation

Many changes in many files, but all functional set under CONFIG_CPU_MIPSR6
preprocessor macro or similar (CONFIG_CPU_MIPS32_R6/CONFIG_CPU_MIPS64_R6).
However, some definitions may be unconditional.

Squashed:
	b3f685f35a1b MIPS: R6 compiler may require "memory" constraint in ASM
	70c9d5dafffe MIPS: R6 buildtool restriction fix
	5bb1b13b4219 MIPS: MIPS R6 basic MAAR support
	17446a9a8be1 MIPS: R6 MAAR bugfix
	9e06287f7d4d MIPS: Support of R6 architecture CP0 changes
	15c77e709963 MIPS: R6: support of separate TLB RI/XI exceptions
	01c3083740e1 MIPS: R6 asm of LL/SC optimization fix
	72535c6169d2 MIPS: R6 - added CM2 L2 Prefetch support
	709763f2eae8 MIPS: R6 emulation of branches
	115e5660aad3 MIPS: R6: fixing jumps in get_frame_info
	cf733bf4aa01 MIPS: R6: removed SPRAM support
	e9656337c82f MIPS: R6: added L2 cache processing
	a92ea7efa46c MIPS: R6 - use SYNCI in trampoline instead of IPI
	57db20cbc0b9 MIPS: Enforce using of ERETNC instead of ERET in MIPS R6
	73c7d199e237 MIPS: R6 bugfix of MIPS32 save/restore on Status.FR1 mode
	a7f651f0c1a6 MIPS: restore CP0_WIRED register handling
	c359d52036c2 MIPS: R6 bugfix of R6 PREF instruction opcode
	b1080dd82704 MIPS: Bugfix of MAAR setup for 2nd core
	a869049afa9e MIPS: R6: memcpy has PREF with offset bigger 256B
	0e5a04a55192 MIPS: R6 bugfix of unaligned handler store
	b1242efec8a5 MIPS: R6: unaligned LWU on MIPS64 R6 should not sign-extend

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>