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(parent: 7abd707) | patch
nvc0: fix unaligned mem access when reading MP counters on Fermi
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Fri, 9 Oct 2015 09:22:20 +0000 (11:22 +0200)
committerSamuel Pitoiset <samuel.pitoiset@gmail.com>
Fri, 16 Oct 2015 19:57:44 +0000 (21:57 +0200)
commitc4896c99cbe10b829981250465baf0b00e18ba40
tree7d434918a651d126688dc266d928a095632466cetree | snapshot
parent7abd707251f29aaf27f83644e47d2dc8b75e10c6commit | diff
nvc0: fix unaligned mem access when reading MP counters on Fermi

Memory access have to be aligned to 128-bits. Note that this
doesn't happen when the card only has TPC.

This patch fixes the following dmesg fail:

gr: GPC0/TPC1/MP trap: global 00000004 [MULTIPLE_WARP_ERRORS] warp 000f
[UNALIGNED_MEM_ACCESS]

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c diff | blob | history
Domain: Graphics System / GL;