[binutils][aarch64] New SVE_ADDR_ZX operand.

[binutils][aarch64] New SVE_ADDR_ZX operand.

Add AARCH64_OPND_SVE_ADDR_ZX operand that allows a vector of addresses
in a Zn register, offset by an Xm register.
This is used with scatter/gather SVE2 instructions.

gas/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (REG_ZR): Macro specifying zero register.
	(parse_address_main): Account for new addressing mode [Zn.S, Xm].
	(parse_operands): Handle new SVE_ADDR_ZX operand.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
	for SVE_ADDR_ZX.
	(aarch64_print_operand): Add printing for SVE_ADDR_ZX.
	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.