riscv: enable software resend of irqs
authorConor Dooley <conor.dooley@microchip.com>
Fri, 29 Jul 2022 11:11:17 +0000 (12:11 +0100)
committerPalmer Dabbelt <palmer@rivosinc.com>
Thu, 13 Oct 2022 18:28:01 +0000 (11:28 -0700)
commitc45fc916c2b2cc2a0587659c18d6ceef9b7299be
tree6ce2de9e6724e0f3a8fbdca8db2855889e479b59
parent5a5294fbe0200d1327f0e089135dad77b45aa2ee
riscv: enable software resend of irqs

The PLIC specification does not describe the interrupt pendings bits as
read-write, only that they "can be read". To allow for retriggering of
interrupts (and the use of the irq debugfs interface) enable
HARDIRQS_SW_RESEND for RISC-V.

Link: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-pending-bits
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Tested-by: Palmer Dabbelt <palmer@rivosinc.com> # on QEMU
Reviewed-by: Björn Töpel <bjorn@kernel.org>
Link: https://lore.kernel.org/r/20220729111116.259146-1-conor.dooley@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/Kconfig