drm/i915/mtl: memory latency data from LATENCY_LPX_LPY for WM
authorRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Thu, 18 Aug 2022 23:41:55 +0000 (16:41 -0700)
committerRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Thu, 25 Aug 2022 21:53:54 +0000 (14:53 -0700)
commitc41aa0204d1c05edadc42e50fdba62784f5841bd
treee0925cfa8c5226e128c0e1b81b17a202b822d84a
parenta2b4cefafa26e6e4dc550366b2caa87a916c179a
drm/i915/mtl: memory latency data from LATENCY_LPX_LPY for WM

Since Xe LPD+, Memory latency data are in LATENCY_LPX_LPY registers
instead of GT driver mailbox.

v2: Use the extracted wm latency adjustment function(Matt)
v3: Use Odd/even for Latency fields(MattR)

Bspec: 64608

Cc: Matt Roper <matthew.d.roper@intel.com>
Original Author: Caz Yokoyama
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/<20220818234202.451742-15-radhakrishna.sripada@intel.com>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_pm.c