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(parent: 1a28d33) | patch
[SelectionDAG] Make getZeroExtendInReg take a vector VT if the operand VT is a vector.
authorCraig Topper <craig.topper@intel.com>
Tue, 7 Apr 2020 18:02:04 +0000 (11:02 -0700)
committerCraig Topper <craig.topper@intel.com>
Tue, 7 Apr 2020 18:34:08 +0000 (11:34 -0700)
commitc41685b16fcceaa2078eb14eb27f6696f851eb49
tree2bac0c72b896ce4312c74e06e9a1b7f78093a58etree | snapshot
parent1a28d33f37f95c76ecba4cf1fc577940bf5e7280commit | diff
[SelectionDAG] Make getZeroExtendInReg take a vector VT if the operand VT is a vector.

This removes a call to getScalarType from a bunch of call sites.
It also makes the behavior consistent with SIGN_EXTEND_INREG.

Differential Revision: https://reviews.llvm.org/D77631
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff | blob | history
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff | blob | history
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp diff | blob | history
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h diff | blob | history
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff | blob | history
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp diff | blob | history
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
Domain: System / Toolchain;