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net/mlx5: Add IFC bits needed for single FDB mode
authorMark Bloch <mbloch@nvidia.com>
Thu, 11 Mar 2021 07:09:14 +0000 (23:09 -0800)
committerSaeed Mahameed <saeedm@nvidia.com>
Fri, 12 Mar 2021 21:07:46 +0000 (13:07 -0800)
commitc3e666f1ada9cbfbe5465f122f9a2d63ddfd25ed
tree2b7d1bac2f8d53f2602eab1a5c0e8e8bb628394dtree | snapshot
parent3a46f4fb55ffd46e475e3fc53b1252f722cf647ecommit | diff
net/mlx5: Add IFC bits needed for single FDB mode

Currently we operate in a mode where each eswitch manager has a separate
FDB. In order to combine these multiple FDBs we expose new caps to allow
this:

- Set root flow table which isn't native.
- Set FDB a different selection mode when in LAG mode.

Signed-off-by: Mark Bloch <mbloch@nvidia.com>
Reviewed-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
include/linux/mlx5/mlx5_ifc.h diff | blob | history
Domain: System / Kernel;