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(parent: 6aa7cc0) | patch
[RISCV][MC] Add support for RV64E
authorJob Noorman <jnoorman@igalia.com>
Thu, 23 Mar 2023 12:17:57 +0000 (12:17 +0000)
committerAlex Bradbury <asb@igalia.com>
Thu, 23 Mar 2023 12:32:25 +0000 (12:32 +0000)
commitc39dd7c1db97fa367cb6282067b74cd8e55ef09a
treee05b477d13931c145000b478da9763186c2e06aatree | snapshot
parent6aa7cc037f2f95c237c1d82c523f8857fa3a10c3commit | diff
[RISCV][MC] Add support for RV64E

Implement MC support for the recently ratified RV64E base instruction
set.

Differential Revision: https://reviews.llvm.org/D143570
26 files changed:
clang/test/Driver/riscv-arch.c diff | blob | history
clang/test/Driver/riscv-features.c diff | blob | history
llvm/docs/RISCVUsage.rst diff | blob | history
llvm/docs/ReleaseNotes.rst diff | blob | history
llvm/lib/Support/RISCVISAInfo.cpp diff | blob | history
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp diff | blob | history
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp diff | blob | history
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp diff | blob | history
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h diff | blob | history
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp diff | blob | history
llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVFeatures.td diff | blob | history
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll [deleted file] blob | history
llvm/test/CodeGen/RISCV/rv32e.ll [deleted file] blob | history
llvm/test/CodeGen/RISCV/rve.ll [new file with mode: 0644] blob
llvm/test/MC/RISCV/attribute-arch.s diff | blob | history
llvm/test/MC/RISCV/elf-flags.s diff | blob | history
llvm/test/MC/RISCV/invalid-attribute.s diff | blob | history
llvm/test/MC/RISCV/mattr-invalid-combination.s [deleted file] blob | history
llvm/test/MC/RISCV/rv32e-invalid.s diff | blob | history
llvm/test/MC/RISCV/rv32e-valid.s diff | blob | history
llvm/test/MC/RISCV/rv64e-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/target-abi-invalid.s diff | blob | history
llvm/test/MC/RISCV/target-abi-valid.s diff | blob | history
llvm/unittests/Support/RISCVISAInfoTest.cpp diff | blob | history
Domain: System / Toolchain;