dt-bindings: phy: tegra: Add Tegra194 support
authorJC Kuo <jckuo@nvidia.com>
Wed, 12 Feb 2020 06:11:31 +0000 (14:11 +0800)
committerThierry Reding <treding@nvidia.com>
Fri, 13 Mar 2020 08:12:40 +0000 (09:12 +0100)
commitc33635708528e7752294ff5b7fb4aa7c3c87b0fe
tree77375b8fa8e254dfdc46d556ab8a7e22cffc18e3
parentcd88f16792011a90aa9cda12233f136a528acab3
dt-bindings: phy: tegra: Add Tegra194 support

Extend the bindings to cover the set of features found in Tegra194.
Note that, technically, there are four more supplies connected to the
XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL)
, but the power sequencing requirements of Tegra194 require these to be
under the control of the PMIC.

Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it
is possible for some platforms have long signal trace that could not
provide sufficient electrical environment for Gen 2 speed. This patch
adds a "maximum-speed" property to usb3 ports which can be used to
specify the maximum supported speed for any particular USB 3.1 port.
For a port that is not capable of SuperSpeedPlus, "maximum-speed"
property should carry "super-speed".

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt