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dt-bindings: riscv: sifive-ccache: Support StarFive JH71x0 SoCs
authorEmil Renner Berthing <kernel@esmil.dk>
Tue, 5 Apr 2022 23:04:45 +0000 (01:04 +0200)
committerŁukasz Stelmach <l.stelmach@samsung.com>
Thu, 9 Feb 2023 18:32:39 +0000 (19:32 +0100)
commitc31b2af9d111e1f25edd1684eda9f957b1b5cd71
treebff047747af515109be15de1bbe25fb5eb0275edtree | snapshot
parent99f9bc4967410d230fc0d1ac6fc9a88d12fddab2commit | diff
dt-bindings: riscv: sifive-ccache: Support StarFive JH71x0 SoCs

This cache controller is also used on the StarFive JH7100 and JH7110
SoCs.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml diff | blob | history
Domain: System / Kernel;