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(parent: 07e70b4) | patch
[DAGCombiner] Preserve the exact bit when simplifying SRA to SRL.
authorBenjamin Kramer <benny.kra@googlemail.com>
Fri, 26 Jun 2015 14:51:49 +0000 (14:51 +0000)
committerBenjamin Kramer <benny.kra@googlemail.com>
Fri, 26 Jun 2015 14:51:49 +0000 (14:51 +0000)
commitc2ae76737753a55f18a290f1e64f8bca60423449
treefdcb984129d8ef3720dfbdc54a2793c5510fe65atree | snapshot
parent07e70b4fa4d6e2504fcd3d6c0b0415e378b937ebcommit | diff
[DAGCombiner] Preserve the exact bit when simplifying SRA to SRL.

Allows more aggressive folding of ashr/shl pairs.

llvm-svn: 240788
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp diff | blob | history
llvm/test/CodeGen/X86/shift-combine.ll diff | blob | history
Domain: System / Toolchain;