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(parent: 8f96dfc) | patch
R600/SI: Update tablegen defs to avoid restoring spilled sgprs to m0
authorTom Stellard <thomas.stellard@amd.com>
Tue, 12 May 2015 15:00:53 +0000 (15:00 +0000)
committerTom Stellard <thomas.stellard@amd.com>
Tue, 12 May 2015 15:00:53 +0000 (15:00 +0000)
commitc274349207e778d088fc7c1eed02c8b4d6993939
tree205dccd6f1d2f370c183eed85ba43ce0b3da8a1ftree | snapshot
parent8f96dfc9eaecccbd090c1e9c9ab4a2bca0e5b729commit | diff
R600/SI: Update tablegen defs to avoid restoring spilled sgprs to m0

We had code to do this in SIRegisterInfo::eliminateFrameIndex(), but
it is easier to just change the definition of SI_SPILL_S32_RESTORE to
only allow numbered sgprs.

llvm-svn: 237143
llvm/lib/Target/R600/SIInstructions.td diff | blob | history
llvm/lib/Target/R600/SIRegisterInfo.cpp diff | blob | history
Domain: System / Toolchain;