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clk: samsung: exynos5420: Add pll_rate_table and clock id for EPLL
authorChanwoo Choi <cw00.choi@samsung.com>
Tue, 29 Dec 2015 01:42:39 +0000 (10:42 +0900)
committerMarek Szyprowski <m.szyprowski@samsung.com>
Mon, 16 May 2016 07:20:41 +0000 (09:20 +0200)
commitc24b99b0dad7eb8a6ff492edbfbc0fc1a7e96e65
tree0a8a74ad8a8ec49553ddb1fcbc986d48343df3f1tree | snapshot
parent4c91efcca43ca51a3e887669bc98054b294fa934commit | diff
clk: samsung: exynos5420: Add pll_rate_table and clock id for EPLL

This patch add the clock id of EPLL to handle it on devicetree file
and the rate tables. EPLL is used as root clock of ASS (Audio Subsystem).

Change-Id: Iefcbd5ea4cb911a3b5d75888286926773a98af54
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
drivers/clk/samsung/clk-exynos5420.c diff | blob | history
include/dt-bindings/clock/exynos5420.h diff | blob | history
Domain: System / Kernel;